Introduction: Why Connect SVA to Software? Seeing an error message in a terminal is fine for a human, but a self-checking testbench needs to know programmatically when an assertion fails. By using the Direct Programming Interface (DPI), we can call a C++ function directly from an SVA “Action Block.” The Action Block: The Trigger Every assertion has two hidden slots called Action Blocks: the “pass” block and the “fail” block. ...
Introduction: Why Decouple? If you embed assertions directly inside your module rtl_logic, you risk two things: Code Bloat Your design files become harder to read. Synthesis Issues While most synthesis tools ignore SVA, keeping them separate ensures there is zero chance of accidentally affecting the hardware gates. Today, we learn the “Wrapper and Bolt” method using the checker and bind constructs. The checker Construct: The Verification Wrapper Think of a checker as a specialized container. It looks like a module, but it is specifically designed to hold assertions, properties, and the modeling logic needed to support them. ...
Introduction: Sequences Define Time In SystemVerilog Assertions, a sequence is a pattern of Boolean expressions that unfolds over one or more clock cycles. Sequences are how you define the temporal relationship between signals. Once a sequence is defined, a property uses it, often along with an implication operator, to establish a clear cause-and-effect rule. 1. Defining Sequences: The Building Blocks The primary tool for defining sequences is the cycle delay operator (##). ...
Introduction: The Two Pillars of SVA SystemVerilog Assertions (SVA) gives you two main ways to check your design’s behavior, depending on the scope of time you need to cover: Immediate Assertions: For checks that must hold true right now, within a single simulation cycle. Concurrent Assertions: For checks that involve time, tracking a sequence of events over multiple clock cycles. Understanding when and where to use each type is crucial for effective verification. ...
Introduction: Why Assertions and Non-Intrusive Verification? SystemVerilog Assertions (SVA) are not just another test language; they are a declarative, temporal powerhouse. Instead of writing hundreds of lines of procedural code to check a protocol’s timing, you define the rule once. This significantly reduces verification effort. In professional flows, it’s crucial to keep verification separate from design. I want to check the golden RTL without modifying it. This post is the first step: setting up the environment using the open-source workhorse Verilator on MacOS system. ...